In a general computing device, the term “copying” means that a processor such as a Central Processing Unit (CPU) reads data from certain memory blocks and writes the data to other memory blocks. General memory copying (or data copying) techniques generally include Programmed Input Output (PIO) and Direct Memory Access (DMA) techniques.
FIG. 1A is a conceptual view of copying data by using the PIO technique according to the related art.
Referring to FIG. 1A, in the case of the PIO technique, a CPU 100 directly repeats load/store data commands until the operation of copying data to be copied is completed. For example, in order to copy data corresponding to memory addresses 0x0 to 0x100 into memory addresses 0x300 to 0x400 of a memory 200, the CPU 100 is generally required to continue to transmit copy commands.
FIG. 1B is a conceptual view of copying data by using the DMA technique according to the related art.
Referring to FIG. 1B, in contrast to the PIO technique, the DMA technique further uses a DMA Controller (DMAC) 110. When data needs to be copied from the memory addresses 0x0 to 0x100 into the memory addresses 0x300 to 0x400 as mentioned in the example above, in the case of the DMA technique, the CPU 100 transmits to the DMAC 110 a command copying source data on memory address 0x0 to 0x100 into destinations, memory addresses 0x300 to 0x400. The DMAC 110 performs data copying on a memory 200. If copying is completed, the DMAC 110 generates an interrupt and notifies the CPU 100 that copying is completed.
FIG. 1C is a conceptual view of a data flow in copying data according to the PIO or DMA technique according to the related art.
Referring to FIG. 1C, the CPU 100 or the DMAC 110 provides a copy data command to a memory controller 180. The command is transmitted through a system bus 102. The memory controller 180 reads data to be copied from the memory 200. The read data is transmitted back to the CPU 100 (e.g., by using the PIO technique) or the DMA controller 110 (e.g., by using the DMA technique) through the system bus 102 and then is written to a target memory block of the memory by the memory controller 180.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present disclosure.